IBM Roadrunner

Roadrunner is a supercomputer built by IBM at the Los Alamos National Laboratory in New Mexico, USA. Currently the world's fastest computer, the US$133-million Roadrunner is designed for a peak performance of 1.7 petaflops, achieving 1.026 on May 25, 2008,and to be the world's first TOP500 Linpack sustained 1.0 petaflops system. It is a one-of-a-kind supercomputer, built from commodity parts, with many novel design features.


A Cell Processor

IBM built the computer for the U.S. Department of Energy's (DOE) National Nuclear Security Administration. It is a hybrid design with 12,960 IBM PowerXCell 8i CPUs and 6,480 AMD Opteron dual-core processors in specially designed server blades connected by Infiniband. The Roadrunner uses the Red Hat Enterprise Linux operating system and is managed with xCAT distributed computing software. It occupies approximately 6,000 square feet (560 m²) and became operational in 2008.

The DOE plans to use the computer for simulating how nuclear materials age in order to predict whether the USA's aging arsenal of nuclear weapons is safe and reliable. Other uses for the Roadrunner include the sciences, financial, automotive and aerospace industries.

Racetrack Memory

Racetrack Memory is an experimental non-volatile memory device under development at IBM's Almaden Research Center by a team led by Stuart Parkin, as well as teams at various other locations. In early 2008 a 3-bit version was successfully demonstrated.

IBM's version of racetrack uses spin-coherent electric current to move the magnetic domains along an U-shaped nanoscopic wire. As current is passing through the wire, the domains move over the magnetic read/write heads positioned at the bottom of the U, which alter the domains to record patterns of bits. A memory device is made up of many such wires and read/write elements. In general operational concept, racetrack memory is similar to the earlier twistor memory or bubble memory of the 1960s and 70s, but uses much smaller magnetic domains and dramatic improvements in magnetic detection capabilities to provide far higher areal densities.

One limitation of the early experimental devices was that the magnetic domains could only be pushed slowly through the wires, requiring current pulses on the orders of microseconds to move them successfully. This was unexpected, and led to performance roughly equal to hard drives, as much as 1000 times slower than predicted. Recent research at the University of Hamburg has traced this problem to microscopic imperfections in the crystal structure of the wires which led to the domains becoming "stuck" at these imperfections. Using an x-ray microscope to directly image the boundaries between the domains, their research found that domain walls would be moved by pulses as short as a few nanoseconds when these imperfections were absent. This corresponds to a macroscopic speed of about 110 m/s.

8b/10b

Original paper by Franaszek and Widmer

In telecommunications, 8b/10b is a line code that maps 8-bit symbols to 10-bit symbols to achieve DC-balance and bounded disparity, and yet provide enough state changes to allow reasonable clock recovery. This means that the difference between the count of 1s and 0s in a string of at least 20 bits is no more than 2, and that there are not more than five 1s or 0s in a row. This helps to reduce the demand for the lower bandwidth limit of the channel necessary to transfer the signal.

The code was described in 1983 by Al Widmer and Peter Franaszek in the IBM Journal of Research and Development. IBM was issued a patent for the scheme the following year. IBM's patent notwithstanding, the method, implementation and goals are very similar to Group Code Recording (GCR) used on floppy disks in some computers during late 1970s/early 80s.

Technologies that use 8b/10b

Now that the IBM patent has expired, the scheme has become even more popular and is the default DC-free line code for new standards.

Among the areas in which 8B/10B encoding finds application are

* PCI Express
* IEEE 1394b
* Serial ATA
* SAS
* Fibre Channel
* SSA
* Gigabit Ethernet (except for the twisted pair based 1000Base-T)
* InfiniBand
* XAUI
* Serial RapidIO
* DVI and HDMI (Transition Minimized Differential Signaling)
* DVB Asynchronous Serial Interface (ASI)
* HyperTransport

Fortran

The Fortran Automatic Coding System for the IBM 704 (October 15, 1956), the first Programmer's Reference Manual for Fortran

Open Directory Fortran

Fortran (previously FORTRAN) is a general-purpose, procedural, imperative programming language that is especially suited to numeric computation and scientific computing. Originally developed by IBM in the 1950s for scientific and engineering applications, Fortran came to dominate this area of programming early on and has been in continual use for over half a century in computationally intensive areas such as climate modeling, Finite Element Analysis, computational fluid dynamics (CFD), computational physics, financial computing, and computational chemistry.



Fortran (a portmanteau derived from The IBM Mathematical Formula Translating System) encompasses a lineage of versions, each of which evolved to add extensions to the language while retaining compatibility with previous versions. Successive versions have added support for processing of character-based data (FORTRAN 77), array programming, module-based programming and object-based programming (Fortran 90 / 95), and object-oriented and generic programming (Fortran 2003).

The legacy of FORTRAN

Since Fortran has been in use for more than fifty years, there is a vast body of Fortran in daily use throughout the scientific and engineering communities. It is the primary language for some of the most intensive supercomputing tasks, such as weather and climate modeling, computational fluid dynamics, computational chemistry, quantum chromodynamics, simulations of long-term solar system dynamics, high-fidelity evolution artificial satellite orbits, and simulation of automobile crash dynamics. Indeed, one finds that even today, half a century later, floating-point benchmarks to gauge the performance of new computer processors are still written in Fortran.

Benoît B. Mandelbrot

Benoît Mandelbrot Wikipedia

Benoît B. Mandelbrot, PhD, (born November 20, 1924) is a Franco-American mathematician, best known as the "father of fractal geometry". He was born in Poland, but his family moved to France when he was a child; he is a dual French and American citizen and was educated in France. Mandelbrot now lives and works in the United States. He is Sterling Professor of Mathematical Sciences, Emeritus at Yale University; IBM Fellow Emeritus at the Thomas J. Watson Research Center; and Battelle Fellow at the Pacific Northwest National Laboratory.

On his retirement from IBM in 1987, Mandelbrot joined the Yale Department of Mathematics. At the time of his retirement in 2005, he was Sterling Professor of Mathematical Sciences. His awards include the Wolf Prize for Physics in 1993, the Lewis Fry Richardson prize of the European Geophysical Society in 2000, the Japan Prize in 2003, and the Einstein Lectureship of the American Mathematical Society in 2006. The small planet 27500 Mandelbrot was named in his honour. On November 23, 1990, he was made a knight in the French Legion of honour.

In 2004, Mandlebrot was given the honor of being the subject of a pop song pop written by Jonathan Coulton.

In December 2005, Mandelbrot was appointed to the position of Battelle Fellow at the Pacific Northwest National Laboratory.

Mandelbrot was promoted to officer of the French Legion of honour on January 1, 2006.

"Clouds are not spheres, mountains are not cones, coastlines are not circles, and bark is not smooth, nor does lightning travel in a straight line."

B.Mandelbrot

Cell

Cell Wikipedia

Cell Broadband Engine resource center

Cell Broadband Engine (SONY)

Cell is a microprocessor architecture jointly developed by a Sony, Toshiba, and IBM, an alliance known as "STI." The architectural design and first implementation were carried out at the STI Design Center over a four-year period beginning March 2001 on a budget reported by IBM as approaching US$400 million. Cell is shorthand for Cell Broadband Engine Architecture, commonly abbreviated CBEA in full or Cell BE in part. Cell combines a general-purpose Power Architecture core of modest performance with streamlined coprocessing elements which greatly accelerate multimedia and vector processing applications, as well as many other forms of dedicated computation.

The first major commercial application of Cell was in Sony's PlayStation 3 game console. Mercury Computer Systems has a dual Cell server, a dual Cell blade configuration, a rugged computer, and a PCI Express accelerator board available in different stages of production. Toshiba has announced plans to incorporate Cell in high definition television sets. Exotic features such as the XDR memory subsystem and coherent Element Interconnect Bus (EIB) interconnect appear to position Cell for future applications in the supercomputing space to exploit the Cell processor's prowess in floating point kernels. IBM has announced plans to incorporate Cell processors as add-on cards into IBM System z9 mainframes, to enable them to be used as servers for MMORPGs.

The Cell architecture includes a novel memory coherence architecture for which IBM received many patents. The architecture emphasizes efficiency/watt, prioritizes bandwidth over latency, and favors peak computational throughput over simplicity of program code. For these reasons, Cell is widely regarded as a challenging environment for software development. IBM provides a comprehensive Linux-based Cell development platform to assist developers in confronting these challenges. Software adoption remains a key issue in whether Cell ultimately delivers on its performance potential. Despite those challenges, research has indicated that Cell excels at several types of scientific computation.

In November 2006, David A. Bader at Georgia Tech was selected by Sony, Toshiba, and IBM from more than a dozen universities to direct the first STI Center of Competence for the Cell Processor. This partnership is designed to build a community of programmers and broaden industry support for the Cell processor.

In 2000, Sony Computer Entertainment, Toshiba Corporation, and IBM formed an alliance ("STI") to design and manufacture the processor.

The STI Design Center in Austin, Texas opened in March 2001. The Cell was designed over a period of four years, using enhanced versions of the design tools for the POWER4 processor. Over 400 engineers from the three companies worked together in Austin, with critical support from eleven of IBM's design centers.

During this period, IBM filed many patents pertaining to the Cell architecture, manufacturing process, and software environment. An early patent version of the Broadband Engine was shown to be a chip package comprising four "Processing Elements," which was the patent's description for what is now known as the "Power Processing Element." Each Processing Element contained 8 "APUs," which are now referred to as SPEs on the current Broadband Engine chip. Said chip package was widely regarded to run at a clock speed of 4 GHz and with 32 APUs providing 32 GFLOPS each, the Broadband Engine was shown to have 1 teraflops of raw computing power.

In March 2007 IBM announced that the 65 nm version of Cell BE is in production at its plant in East Fishkill, New York.

OpenDX

OpenDX

OpenDX is a uniquely powerful, full-featured software package for the visualization of scientific, engineering and analytical data: Its open system design is built on a standard interface environments. And its sophisticated data model provides users with great flexibility in creating visualizations.