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25 Eylül 2010 Cumartesi

Memristor


An array of 17 purpose-built oxygen-depleted titanium dioxide memristors built at HP Labs, imaged by an atomic force microscope. The wires are about 50 nm, or 150 atoms, wide. Electric current through the memristors shifts the oxygen vacancies, causing a gradual and persistent change in electrical resistance.

A memristor (a portmanteau of "memory resistor") is a passive two-terminal circuit element in which the resistance is a function of the time history of the current and voltage through the device. Memristor theory was formulated and named by Leon Chua in a 1971 paper.

On April 30, 2008 a team at HP Labs announced the development of a switching memristor. Based on a thin film of titanium dioxide, it has a regime of operation with an approximately linear charge-resistance relationship. These devices are being developed for application in nanoelectronic memories, computer logic, and neuromorphic computer architectures.

A memristor is a passive two-terminal electronic component for which the resistance (dV/dI) is proportional to the amount of charge that has flowed through the circuit. When current flows in one direction through the device, the resistance increases; and when current flows in the opposite direction, the resistance decreases. When the current is stopped, the component retains the last resistance that it had, and when the flow of charge starts again, the resistance of the circuit will be what it was when it was last active.

More generally, a memristor is a two-terminal component in which the resistance depends on the integral of the input applied to the terminals, rather than on the instantaneous value of the input at the terminals. Since the element "remembers" the amount of current that has passed through it in the past, it was tagged by Chua with the name "memristor." A general memristor is any of various kinds of passive two-terminal circuit elements that maintain a functional relationship between the time integrals of current and voltage. This function, called memristance, is similar to variable resistance. Specifically engineered memristors provide controllable resistance, but such devices are not commercially available. Other devices such as batteries and varistors have memristance, but it does not normally dominate their behavior. The definition of the memristor is based solely on fundamental circuit variables, similar to the resistor, capacitor, and inductor. Unlike those three elements, which are allowed in linear time-invariant or LTI system theory, memristors are nonlinear and may be described by any of a variety of time-varying functions of net charge. There is no such thing as a generic memristor. Instead, each device implements a particular function, wherein either the integral of voltage determines the integral of current, or vice versa. A linear time-invariant memristor is simply a conventional resistor.

In his 1971 paper, memristor theory was formulated and named by Leon Chua, extrapolating the conceptual symmetry between the resistor, inductor, and capacitor, and inferring that the memristor is a similarly fundamental device. Other scientists had already proposed fixed nonlinear flux-charge relationships, but Chua's theory introduced generality.

Like other two-terminal components (e.g., resistor, capacitor, inductor), real-world devices are never purely memristors ("ideal memristor"), but will also exhibit some amount of capacitance, resistance, and inductance.

Williams' solid-state memristors can be combined into devices called crossbar latches, which could replace transistors in future computers, taking up a much smaller area.

They can also be fashioned into non-volatile solid-state memory, which would allow greater data density than hard drives with access times potentially similar to DRAM, replacing both components. HP prototyped a crossbar latch memory using the devices that can fit 100 gigabits in a square centimeter, and has designed a highly scalable 3D design (consisting of up to 1000 layers or 1 petabit per cm3).[7] HP has reported that its version of the memristor is currently about one-tenth the speed of DRAM. The devices' resistance would be read with alternating current so that the stored value would not be affected.

Some patents related to memristors appear to include applications in programmable logic, signal processing, neural networks, and control systems.

Recently, a simple electronic circuit consisting of an LC network and a memristor was used to model experiments on adaptive behavior of unicellular organisms. It was shown that the electronic circuit subjected to a train of periodic pulses learns and anticipates the next pulse to come, similarly to the behavior of slime molds Physarum polycephalum subjected to periodic changes of environment. Such a learning circuit may find applications, e.g., in pattern recognition.

11 Temmuz 2010 Pazar

NonStop


Tandem NonStopII System (1981)

NonStop can refer to the line of HP Integrity NonStop computers, the line of Tandem NonStop computers that preceded them, or the NonStop OS operating system that is designed for them. NonStop systems are based on an integrated hardware/software stack. They are self-healing systems designed with redundant components and automatic reconfiguration in the event of a component failure, to prevent against "single-point failures". The systems run the NonStop OS operating system and the database management systems NonStop SQL and Enscribe.

Originally introduced in 1976 by Tandem Computers Inc., the line was later owned by Compaq (from 1997) and Hewlett-Packard (since 2003). In 2005, the current product line of HP Integrity NonStop servers, based on Intel Itanium microprocessors, was introduced.

Early NonStop applications had to be specially coded to be fault-tolerant. That obstacle was removed in 1983 with the introduction of the Transaction Monitoring Facility (TMF), which handles the various aspects of fault tolerance on the system level, transparent to the application.

NonStop OS

NonStop OS is a message-based operating system designed for software fault tolerance. It works with process pairs and ensures that backup processes in different CPU's take over in case of a process or CPU failure. Data integrity is maintained during those takeovers, no transactions or data are lost or corrupted.

NonStop Hardware

The HP Integrity NonStop computers are a line of fault-tolerant server computers, optimized for transaction processing and providing an extreme level of availability and data integrity. Average availability levels of 99.999% have been observed. NonStop systems feature a massive parallel processing (MPP) architecture and provide linear scalability. Each CPU (systems can be expanded up to over 4000 CPUs) runs its own copy of the OS. This is a "share nothing" arrangement and no "diminishing returns" occur as more processors are added.

Due to the integrated hardware/software stack and a single system image for even the largest configurations, system management requirements for NonStop systems are rather low. In most deployments there is just a single production server, not a complex server farm.

Most customers also have a backup server in a remote location for disaster recovery. There are standard products to keep the data of the production and the backup server in sync, hence there is fast takeover and no data loss also in a disaster situation with the production server being disabled or destroyed.

NonStop systems are inherently very secure, no security breach by outside hackers has been reported so far.

HP also developed a data warehouse and business intelligence server line, HP Neoview, based on the NonStop line. It acts as a database server, providing NonStop OS and NonStop SQL, but lacks the transaction processing functionality of the original NonStop systems.

4 Ekim 2008 Cumartesi

Intel Itanium



Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel has released two processor families using the brand: the original Itanium and the Itanium 2. Starting November 1, 2007, new members of the second family are again called Itanium. The processors are marketed for use in enterprise servers and high-performance computing systems. The architecture originated at Hewlett-Packard (HP) and was later developed by HP and Intel together.



Itanium's architecture differs dramatically from the x86 architectures (and the x86-64 extensions) used in other Intel processors. The architecture is based on explicit instruction-level parallelism, with the compiler making the decisions about which instructions to execute in parallel. This approach allows the processor to execute up to six instructions per clock cycle. By contrast with other superscalar architectures, Itanium does not have elaborate hardware to keep track of instruction dependencies during parallel execution - the compiler must keep track of these at build time instead.

After a protracted development process, the first Itanium was released in 2001, and more powerful Itanium processors have been released periodically. HP produces most Itanium-based systems, but several other manufacturers have also developed systems based on Itanium. As of 2007, Itanium is the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, IBM POWER, and SPARC. Intel released its newest Itanium, codenamed Montvale, in November 2007.

Intel has extensively documented the Itanium instruction set and microarchitecture, and the technical press has provided overviews. The architecture has been renamed several times during its history. HP called it PA-WideWord. Intel later called it IA-64, then Itanium Processor Architecture (IPA), before settling on Intel Itanium Architecture, but it is still widely referred to as IA-64. It is a 64-bit register-rich explicitly-parallel architecture. The base data word is 64 bits, byte-addressable. The logical address space is 2^64 bytes. The architecture implements predication, speculation, and branch prediction. It uses a hardware register renaming mechanism rather than simple register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops. Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture.

The architecture implements 128 integer registers, 128 floating point registers, 64 one-bit predicates, and eight branch registers. The floating point registers are 82 bits long to preserve precision for intermediate results.

7 Eylül 2007 Cuma

HP iPAQ 210 Enterprise PDA



HP iPAQ 210 Enterprise PDA Official

Specifications

HP iPAQ 210 First Thoughts

Highlights:

* Processor: Marvell PXA310, 624 MHz
* ROM: 256MB
* RAM: 128MB for running applications
* Display: 4-inch VGA TFT with touch screen, portrait oriented
* Wireless LAN: IEEE 802.11b/g1
* Bluetooth: v2.0 with EDR1
* Connectors: 24-pin connector and Mini USB
* Battery: 2200 mAh
* Expansion: SDIO (high-capacity), CF
* Headphone jack: 3.5mm 4-pin
* Speaker: 2
* Microphone: 1
* Input: touch, stylus
* Buttons: 5-way navigation with press to activate, 4 programmable, voice recorder, power, reset
* LED: 8
* Operating System: Windows Mobile® 6 Classic Edition